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NSD-1202 dual piezo motor driver ic for sql series squiggle motors www.austriamicrosystems.com/NSD-1202 revision 0.2 1 - 13 data sheet 1 general description the NSD-1202 is a dedicated piezo motor driver asic capable of driving two sql series squiggle motors from a single 2.8 to 5.5 vdc supply. the two motors can be controlled independently using a standard i2c interface. an on-chip dc-dc step-up converter generates the high supply voltage (24 to 40 vdc) required by the piezoelectric elements of the squiggle motor. four half bridge drivers create pairs of phase-shifted square waves with ultrasonic frequency as required to drive sql series squiggle motors. figure 1. NSD-1202 functional block diagram 2 key features wide input supply voltage range: 2.8 to 5.5vdc step-up converter to generate programmable high-voltage power supply (24 to 40v) minimum 65% efficiency (at vdd=2.8v, i out =25ma, freq=2mhz) 4x output driver with defined rise/fall time i2c interface on chip registers store driver instructions power-down mode for minimal power consumption in stand-by small 4x4mm 16-pin qfn package this part supersedes and is backward-compatible with the nsd- 1102. 3 applications the NSD-1202 is ideal for squiggle piezoelectric motor driver. vddh lx vssp drv2p2 drv1p1 drv1p2 NSD-1202 trim level- shifter level- shifter level- shifter level- shifter logic i2c interface voltage reference registers 1 1 1 1 step-up controller scl adr clk drv2p1 sda vss xpd vdd (2.8-5.5v) vin (2.8-5.5v) c1 22f l1 4.7h d1 vddh (programmable 24v...40v) c2 1f ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 2 - 13 NSD-1202 data sheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin name pin number pin type character description vddh 1 supply pad power high voltage supply adr 2 digital input input slave address input lx 3 analog i/o output power output to inductor vdd 4 supply pad power low voltage supply vss 5 gnd signal ground clk 6 digital input input 20mhz clock input sda 1 1. sda (data io) and scl (data clock) constitute an i2c interface. both have open drain outputs. 7 digital i/o bidir data io scl 1 8 data clock (400 khz max) xpd 9 digital input input power down, active low vssp 10 supply pad gnd power ground nc11 11 digital i/o bidir test mode pin, connect to vss nc12 12 analog i/o test io pin, connect to vss drv1p2 13 output half bridge 1 phase2 output drv1p1 14 half bridge 1 phase 1 output drv2p2 15 half bridge 2 phase2 output drv2p1 16 half bridge 2 phase1 output 16 1 2 3 4 12 11 10 9 15 14 13 5 6 7 8 nc nc vssp xpd vddh adr lx vdd vss clk sda scl drv1p2 drv1p1 drv2p2 drv2p1 NSD-1202 ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 3 - 13 NSD-1202 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 4 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings symbol parameter min typ max units comments v vdd voltage at low voltage supply pin -0.3 7 v internal 3.3v supply (vdda) v vddh voltage at high voltage supply pin -0.3 50 v high voltage supply v lx voltage at lx pin -0.6 v vddh +0 .3 v v lv voltage at clk, sda, scl, xpd -0.3 7 v low voltage pads iscr input current (latchup immunity) -50 50 ma norm: jedec 78 esd electrostatic discharge 1 kv norm: mil 883 e method 3015 human body model: r=1.5k , c=100pf ptot total power dissipation 1w rthja thermal resistance qfn16 4x4mm 29.7 33 36.3 k/w tstrg storage temperature -40 150 oc tbody soldering temperature 260 oc norm: ipc/jedec j-std-020c. the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020c ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. humidity non-condensing 585% ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 4 - 13 NSD-1202 data sheet - electrical characteristics 6 electrical characteristics 6.1 electrical syst em specifications all system parameters are guaranteed up to 125oc junction temperature unless explicitly mentioned. table 3. operating conditions symbol parameter conditions min typ max units v vdd voltage at vdd vdd rise time is between 10s and 100ms 2.8 5.5 v v vddh voltage at vddh high voltage supply 24 40 v v lx voltage at lx pin -0.6 v vddh +0.3 v v vssp voltage at vssp gnd reference for step up converter -0.3 0.3 v v vss voltage at vss gnd reference potential 0 0 v v lv voltage at clk, sda,scl, xpd low voltage pads -0.3 5.5 v t amb ambient temperature -40 85 oc table 4. electrical system specifications parameter conditions min typ max units vdd 2.8 3.3 5.5 v ambient temperature -40 +85 oc junction temperature -40 +125 oc stand-by current consumption xpd=low, temp=27oc; no activity on i2c interface and clk static 5 a operating current consumption xpd=high, step-up converter on but not running a motor 1.5 ma output voltage (vddh) default value is 35v after start-up 24 40 v output voltage (vddh) steps 0.5 v output voltage accuracy -6 +6 % hysteresis 0.325 0.5 0.675 v output current dc 25 ma efficiency v in =2.8v, efficiency calculations assume the use of the components as specified in the applications description section (see page 6) 65 % ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 5 - 13 NSD-1202 data sheet - electrical characteristics 6.2 dc/ac characteristics for digital inputs and outputs table 5. cmos input: xpd, adr, clk symbol parameter conditions min typ max units v ih high level input voltage 1.2 vdd v v il low level input voltage vss 0.3 v i leak input leakage current 1a c in capacitive load 15 pf table 6. cmos i2c interface: sda, scl symbol parameter conditions min typ max units v ih high level input voltage 1.2 vdd v v il low level input voltage vss 0.3 v i leak input leakage current 1a v oh high level output voltage depending on external pull-up resistor v vdd -0.5 v vdd v v ol low level output voltage @3ma output current vss+0.4 v c l capacitive load: sda, scl 50 pf r pu external pull-up resistor: sda, scl as defined by i2c spec 1.2 6.0 7.1 k scl i2c write frequency maximum clock frequency to write data 400 khz ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 6 - 13 NSD-1202 data sheet - detailed description 7 detailed description figure 1 shows the main building blocks of the system: voltage reference step up converter i2c interface registers selectable feedback four (4) half bridge drivers supplementary blocks such as biasing or power-on reset are not shown. the step-up converter is built as a hysteretic step-up co nverter. the half bridge drivers operate rail to rail (vssp to vddh). user suppli ed external components c1, c2, l1 and d1 provide voltage boost a nd regulation. the output voltage can be programmed via the i2c interface in 0.5v steps between 24v and 40v. this voltage, along with the duty cycle (or pulse width) of the drive signal, determines the speed of the motor. registers define the switching frequency of the motor, which can be dynamically adjusted from 140 khz to 180 khz for optimum mo tor performance. other registers control motor direction and the number of pulses the motor is active (correlating to distance trav eled). the xpd input enables a stand-by mode. 7.1 step up converter the internal switching converter, together with l1 and c2, form a step up dc/dc converter used to create the high level voltage vddh in the range 24 to 40v. the switch includes an over-current detect circuit to ensure safe operation at all times. the output voltage c an be programmed via i2c interface in steps of 0.5v from 24v to 40v. at power up the default output voltage is set to 35v. 7.2 i2c the i2c interface is used to control the NSD-1202 and set the value of several registers. these registers will define the outpu t voltage (by changing the resistive feedback divider) as well as the direction and duration of the output driver signals. the period count. duty cycle (or pulse width) and pulse count registers can be set separately for each motor. start/stop condition: a high to low transition on the sda line while scl is high is the start condition for the bus. a low to high transition on the sda line while scl is high is the stop condition. every byte put on the sda line must be 8-bits long. each byte mu st be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. data transfer with acknowledge is obligatory. the acknowledge-related clock pulse is generated by the master. the receiver must pull down the sda line during the acknowledge clock pulse. the NSD-1202 is a slav e device on the bus. there are two different access modes: -byte write - page write the device can be addressed using 7-bit addressing. the first 6 bits are fixed. the last bit can be set via package pin. provis ion will be made for data collision due to non-synchronization between the external clock and the internally generated clock. ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 7 - 13 NSD-1202 data sheet - detailed description 7.3 register map the table below shows the registers which can be addressed over the i2c interface. 7.4 output drivers the output drivers operate rail to rail and are capable of driving a large capacitive load. in power-down mode the output drive rs are pulled to ground. the same applies when the motor is off. description address data byte msb lsb period count a 00h xxxxxxxx pulse count a (high byte) 1 1. the master clock doubling bit (?h?) of both registers 01h and 04h must set in order for the doubling to take affect (even if only driving one motor). do not use clock doubling if the master clock has a frequency > 10 mhz. 01h hd xxx pulse count a (low byte) 02h xxxxxxxx period count b 03h xxxxxxxx pulse count b (high byte) 1 04h hd xxx pulse count b (low byte) 05h xxxxxxxx output voltage 06h xxxxxx duty cycle a 07h xxxxxxxx duty cycle b 08h xxxxxxxx reserved register 10h xxxxxxxx symbol parameter conditions min typ max units rise/fall time c load 600pf 25 100 250 ns c load load capacitance the load capacitance may be lower than 500pf but the lower the value the shorter the rise time. 500 600 700 pf switching frequency the accuracy of switching frequency and phase shift will be defined depending on master clock frequency; the given values are for 20mhz master clock. lower master clock frequencies give higher deviations. for squiggle applications 20mhz clock is required, 10 mhz can be used with the clock doubling feature. 140 170 180 khz switching frequency step 0.98 1.45 1.61 khz switching frequency duty cycle 150% duty cycle accuracy -1 +1 % phase shift 90 deg phase shift error 3 deg master clock frequency (clk) clock doubling feature may be employed when using a 10mhz or less master clock frequency 12020mhz ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 8 - 13 NSD-1202 data sheet - detailed description 7.5 period counter the period counter is used to define the switching frequency of the motor. the pulse period is generated by dividing the clock input frequency by the given period counter value. the msb of the high byte of the pulse counter (h) is used to enable the internal frequency doubler. this function should be use d only for input clock frequencies of 10mhz or less. at 20mhz input clock a decimal period counter value of 111 gives an output frequency of 180 .18 khz. a period counter value of 112 results in a switching frequency of 178.75 khz. this is equal to a maximum frequency step of 1.61 k hz. the frequency resolution gets better for lower output frequencies, assuming a fixed input clock frequency. the following table presents examples of the period counter and output switching frequency relationship. the values are given f or 20mhz and 10mhz clock input frequency. (at 10mhz the frequency doubler can be activated, which leads to the same results.) 7.6 pulse counter the pulse counter sets the number of pulses the motor should be active. writing all zeros to the pulse counter stops the motor, even if the previous set counter value is not completed. all outputs are then low. the same is valid for power-down mode. bit 6 of the high byte in the pulse counter (d) is used to set the direction of motor motion. 7.7 output vo ltage register this register is used to define the output voltage of the boost converter. the register value is directly transferred to the an alog part. the default value for this register set during power up or power down (xpd = low) is equal to 35v nominal output voltage. varying the output voltage can be used to vary the speed of the motor. however, if two motors are being driven, both motors use a common output voltage and therefore one setting applies to both motors. to control the speed of two motors independently, use the duty cycle register. period counter value typ unit 0110 1111 180.18 khz 0111 0000 178.57 khz 1000 0101 150.37 khz 1000 0110 149.25 khz 1000 1110 140.85 khz 1000 1111 139.86 khz pulse counter value typ unit conditions xxxx x000 0000 0000 0 pul ses motor is off, driver outputs are low xxxx x100 0000 00 00 1024 pulses xxxx x111 1111 1111 2047 pulses maximum possible number of pulses output voltage register typ unit conditions 0001 0001 24.0 v 0001 0010 24.5 v 0001 1111 31.0 v 0010 0111 35.0 v default value 0011 0000 39.5 v 0011 0001 40.0 v ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 9 - 13 NSD-1202 data sheet - detailed description 7.8 duty cycle register a register is used to define the duty cycle (or pulse width) of the driver output signal for each motor. the register value is directly transferred to the analog part. since changing the duty cycle will change the speed of the motor, this register can be used to control the speed of two motors independently. (motor speed can also be controlled by varying the voltage; however, one setting applies to both motors. see the previous secti on, output voltage register.) to provide motor independent speed control, the duty cycle may be adjusted from 50% (max speed) down to ~12% (minimum speed). a lower duty cycle could be used, but may not provide enough vibration amplitude to overcome the load. the default value for this register set during power up or power down (xpd = low) is equal to 00h. in this case the default dut y cycle of 50% is generated. the resulting duty cycle and resolution of single steps is depending on the master clock frequency and the switching frequency of the driver output. in the following table an example for 20mhz clock input and 150khz driver frequency is given. the value of the duty cycle regis ter should not exceed 50% of the period counter value. duty cycle register min typ max unit 0000 0000 49.6/50.4 % 0000 0001 0.8 % 0000 1101 9.8 % 0001 1011 20.3 % 0010 1000 30.1 % 0011 0101 39.8 % 0100 0010 49.6 % 0100 0011 50.4 % ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 10 - 13 NSD-1202 data sheet - application information 8 application information the NSD-1202 is designed to drive two sql-1.8 squiggle motors. recommended external components are as follows: new scale offers a convenient mc-33db evaluation board which includes these components, along with input and motor connectors, to take full advantage of the NSD-1202 asic. the xpd input can be used to place the asic in stand-by mode for minimal current consumption when the motor is not moving. alte rnatively, the designer can implement an external switch to power off the asic completely when the motor is not moving: the squiggle motor hol ds its position with the power off. component description manufacturer part number wxlxh [mm] c1 22f cap 6.3v www.murata.com grm21br60j226me39 1.25x2.0x1.25 c2 1f cap 50v grm21br71h105ka12 1.25x2.0x1.25 l1 4.7h inductance www.coilcraft.com epl2014-472 2.0x2.0x1.4 d1 diode www.nxp.com pmeg6010cej 1.25x2.5x0.80 drv2p1 drv2p2 drv1p1 drv1p2 vddh lx vssp drv2p2 drv1p1 drv1p2 NSD-1202 trim level- shifter level- shifter level- shifter level- shifter logi c i2c interface voltage referenc e register s 1 1 1 1 step-up controlle r scl adr clk drv2p1 sda vss xpd vdd (2.8-5.5v) vin (2.8-5.5v) c1 22f l1 4.7h d1 vddh (programmable 24v...40v) c2 1f NSD-1202 dual piezo motor driver ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 11 - 13 NSD-1202 data sheet - pack age drawings and markings 9 package drawings and markings the devices are available in a 16ld qfn (4x4mm) package. figure 3. 16ld qfn (4x4mm) package drawings and dimensions notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters, angle is in degrees. 3. dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. dimension l1 repres ents terminal full back from package edge up to 0.1mm is acceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional. symbol min nom max a 0.75 0.85 0.95 a1 0.203 ref b 0.25 0.30 0.35 d 4.00 bsc e 4.00 bsc d2 2.30 2.40 2.50 e2 2.30 2.40 2.50 symbol min nom max e 0.65 bsc l 0.40 0.50 0.60 l1 0.10 p 45o bsc aaa 0.15 ccc 0.10 #1 2 3 4 56 7 8 9 10 11 12 16 15 14 13 ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 12 - 13 NSD-1202 data sheet - ordering information 10 ordering information the devices are available as the standard products shown in table 7 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 7. ordering information ordering code description delivery form package NSD-1202bqft dual piezo motor driver ic tape & reel qfn-16 (4x4mm) ams ag technical content still valid
www.austriamicrosystems.com/NSD-1202 revision 0.2 13 - 13 NSD-1202 data sheet - copyrights copyrights copyright ? 1997-2010, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact contact information new scale technologies, inc. 121 victor heights parkway victor, ny 14564 tel: +1 585 924 4450 fax: +1 585 924 4468 sales@newscaletech.com www.newscaletech.com ams ag technical content still valid

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